Low-Noise Low-Power Design for Phase-Locked Loops
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- Synopsis
- This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
- Copyright:
- 2015
Book Details
- Book Quality:
- Publisher Quality
- ISBN-13:
- 9783319122007
- Publisher:
- Springer International Publishing, Cham
- Date of Addition:
- 10/17/16
- Copyrighted By:
- Springer
- Adult content:
- No
- Language:
- English
- Has Image Descriptions:
- No
- Categories:
- Nonfiction, Technology
- Submitted By:
- Bookshare Staff
- Usage Restrictions:
- This is a copyrighted book.